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fix: correct SCB1 clock divider for PSoC Edge UART - #47
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Except the "default" PR message it looks good ;) |
djaumann
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Ah it is a draft ... never mind |
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Use and enable PERI0 group 8 instead of group 1.
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Description
Serial1 could not send or receive data.
SCB1 is clocked from clk group 8, but the overlay assigned it a group-1 divider (peri0_group1_16bit_0), and the group-8 divider was never enabled. As a result, SCB1 had no clock.
So this PR assigns and enables clock to scb1.
With this fix:
fixed tests: wait_and_read_one_byte, wait_and_peek, wait_and_read_multi_bytes, wait_and_read_in_loop, wait_for_println, read_longer_than_writable, check_no_available_read_peek, write_reply_back
Issue: (unrelated to this commit)
tx not_ready, tx end, rx end fails. Serial1 always reports true, but the tests expect false before begin() and after end().
tx availableForWrite also fails expects 0
this will be handled in a follow up PR